Optical transmission system, fec multiplexer, fec multiplexer/separator, and error correction method

ABSTRACT

An FEC multiplexing circuit ( 2 ) has a configuration in which a first memory circuit ( 15 ) is arranged on the input stage of a first RS encoding circuit ( 16 ), a second memory circuit ( 17 ) is arranged on the input stage of a second RS encoding circuit ( 18 ), error correction encoding is performed by a combination of different data having two directions, and thereafter, error correction codes are multiplexed to generate an FEC frame. On the other hand, an FEC demultiplexing circuit ( 6 ) has a configuration in which a third memory circuit ( 42 ) is arranged on the output stage of a first RS decoding circuit ( 41 ), a fourth memory circuit ( 44 ) is arranged on the output stage of a second RS decoding circuit ( 43 ), error correction is performed by a combination of different data having two directions, and, thereafter, parallel data read from the fourth memory circuit ( 44 ) are multiplexed to reproduce original information data.

TECHNICAL FIELD

[0001] The present invention relates to an optical transmission systemthat corrects bit errors using FEC (For Error Correction) method.Particularly, this invention relates to an optical transmission systemwhich realizes long-distance and large-capacity transmission byperforming error correction using FEC method, an FEC multiplexing devicethat is a part of the optical transmission system, an FEC demultiplexingdevice, and a method of correcting error.

BACKGROUND ART

[0002] A conventional optical transmission system will be describedbelow. As a conventional optical transmission system using FEC, a systemachieved by a combination of an FEC multiplexing device and an FECdemultiplexing device described in ITU-T Recommendation G. 975 is known.FIG. 7(a) shows the configurations of the FEC multiplexing device, andFIG. 7(b) shows the configurations of the FEC demultiplexing devicedescribed in the above reference.

[0003] In FIG. 7(a), reference numeral 101 denotes a firstdemultiplexing circuit, reference numeral 102 denotes a seconddemultiplexing circuit, reference numeral 103 denotes a first ratecharging circuit, reference numeral 104 denotes an OH insertion circuit,reference numeral 105 denotes an RS encoding circuit, reference numeral106 denotes a first multiplexing circuit, and reference numeral 107denotes a second multiplexing circuit. In FIG. 7(b), reference numeral111 denotes a third demultiplexing circuit, reference numeral 112denotes a fourth demultiplexing circuit, reference numeral 113 denotes aframe synchronizing circuit, reference numeral 114 denotes an RSdecoding circuit, reference numeral 115 denotes an OH separationcircuit, reference numeral 116 denotes a second rate change circuit 116,reference numeral 117 denotes a third multiplexing circuit, andreference numeral 118 denotes a fourth multiplexing circuit.

[0004] The operations of the FEC multiplexing device and the FECdemultiplexing device will be described below. The first demultiplexingcircuit 101 which receives STM-16 data (2.5 Gbit/s) demultiplexes 16parallel data (156 Mbit/s), and the second demultiplexing circuit 102demultiplexes the received 16 parallel data into 128 parallel data (19Mbit/s)

[0005] The first rate charging circuit 103 which receives the 128parallel data adds redundant data regions to the data to generate 128redundant parallel data (21 Mbit/s) The OH insertion circuit 104 insertsoverhead information (e.g., frame synchronous information or the like)required to maintain/operate an optical transmission system into the 128redundant parallel data. The RS (255, 239) encoding circuit 105 performserror correction encoding to an output from the OH insertion circuit104.

[0006] The first multiplexing circuit 106 multiplexes the received datasubjected to the error correction encoding into 16 parallel data (167Mbit/s), and the second multiplexing circuit 107 generates an FEC frame(2.66 Gbit/s) from the 16 received parallel data.

[0007] On the other hand, the third demultiplexing circuit 111 of theFEC demultiplexing device which receives the FEC frame demultiplexes theframe into 16 parallel data (167 Mbit/s), and the fourth demultiplexingcircuit 112 demultiplexes the 16 received parallel data into 128parallel data (21 Mbit/s)

[0008] The frame synchronizing circuit 113 detects the start position ofthe FEC frame from the from synchronous information stored in the OH inthe 128 received parallel data. The RS (255, 239) decoding circuit 114detects an error of the data in the FEC frame and corrects the data intothe original correct data.

[0009] The OH separation circuit 115 separates an OH from the correcteddata, and the second rate change circuit 116 reduces the redundantregions to generate 128 parallel data (19 Mbit/s). The thirdmultiplexing circuit 117 multiplexes the 128 received parallel data into16 parallel data (156 Mbit/s), and the fourth multiplexing circuit 118demodulates the original STM-16 data (2.5 Gbit/s) from the 16 receivedparallel data.

[0010]FIG. 8 includes diagrams showing the configurations of FEC framesgenerated by the FEC multiplexing device. The FEC frame is constitutedby sub-frames 1 to 128 including one column of OH information, 238columns of STM-16 data, and 16 columns of RS redundant data. Forexample, error correction encoding is performed every 8 sub-frames. Morespecifically, in the sub-frame 1 to 8, error correction code calculationis performed to the OH information and the STM-16 data, and RS (255,239) redundant data are stored in R0-0 to R0-15 (see FIG. 8(a)). The FECframe is generated by sequentially multiplexing the sub-frames 1 to 128(see FIG. 8(b)). Reference symbol f (integer) in the FEC frame in FIG.8(b) denotes the number of times of multiplexing of an RS code. FIG.8(b) shows a case in which f=16 is satisfied.

[0011] In the FEC frame, since a transmission rate increases a ratewhich is 15/14 (255/238) the rate of the original STM-16 data, thetransmission rate is 2.69 Gbit/s.

[0012] In this manner, in the conventional optical transmission system,the FEC frame is constituted as described above to make it possible tocorrect bit errors. As a result, high-quality service can be offeredeven if optical SNR decreases in the optical transmission system. Ingeneral, an RS (255, 239) code shown in FIG. 8 is changed into an RS(127, 111) code in which, for example, an error correction code lengthis reduced, i.e., the columns of the STM -16 data is changed from 238 to110 (arbitrary integer equal to or smaller than 237) to increase theratio of redundant information to information data, so that errorcorrection capability can be more improved.

[0013] However, the conventional optical transmission system has thefollowing problems. For example, when a distance for which transmissionis to be performed is increased gradually, or when the number ofwavelengths in a wavelength multiplexing system is increased gradually,so also the optical SNR deteriorates gradually. For this reason, thecode length of an error correction code is reduced to maintain the errorcorrection capability to some extent. On the other hand, when the codelength of the error correction code is reduced, a ratio of redundantinformation to information data increases. For this reason, atransmission rate increases in accordance with the increase of theratio. For example, when the rate of the STM-16 data is 2.5 Gbit/s, thetransmission rate of an FEC frame subjected to RS (127, 111) encoding is2.89 Gbit/s which is 127/110 times the rate of the STM-16 data.

[0014] For this reason, in the conventional optical transmission system,even though the code length of an error correction code is reduced tomaintain error correction capability, an amount of deterioration ofoptical transmission characteristics is increased with an increase inrate, a long-distance/large-capacity optical transmission system havingdesired quality cannot be structured.

[0015] It is an object of the present invention to provide an opticaltransmission system which can improve error correction capability eventhough an amount of deterioration of optical transmissioncharacteristics with an increase in rate. It is another object of thisinvention to provide an FEC multiplexing device constituting the opticaltransmission system, an FEC demultiplexing device, and a method ofcorrecting error.

DISCLOSURE OF THE INVENTION

[0016] The optical transmission system according to one aspect of thepresent invention comprises an FEC generation section (corresponding toan FEC multiplexing circuit 2 according to an embodiment to be describedlater) which generates and outputs an FEC frame, and an error correctionsection (corresponding to an FEC demultiplexing circuit 6) whichperforms error correction based on the FEC frame. The FEC generationsection includes a first reading unit (corresponding to a first memorycircuit 15) which sequentially stores first parallel data generated bydemultiplexing information data and, thereafter, changes the order ofthe storage data on the basis of a predetermined standard to read thedata, a first encoding unit (corresponding to a first RS encodingcircuit 16) which performs first error correction encoding to the readdata to generate first error correction codes, a second reading unit(corresponding to a second memory circuit 17) which sequentially storesthe first error correction codes and, thereafter, changes the order ofthe stored data into the original data to read the data, a secondencoding unit (corresponding to a second RS encoding circuit 18) whichperforms second error correction encoding to the read data to generatesecond error correction codes, and a frame generation unit(corresponding to a first multiplexing circuit 19 and a secondmultiplexing circuit 20) which multiplexes the second error correctioncodes to generate an FEC frame. The error correction section includes afirst error correction unit (corresponding to a first RS decodingcircuit 41) which performs error correction by a first decoding processto second parallel data generated by demultiplexing the FEC frame, athird reading unit (corresponding to a third memory circuit 42) whichsequentially stores the parallel data subjected to the first decodingprocess and, thereafter, changes the order of the stored data on thebasis of a predetermined standard to read the data, second errorcorrection unit (corresponding to second RS decoding circuit 43) whichperforms error correction by a second decoding process to the readparallel data, a fourth reading unit (corresponding to a fourth memorycircuit 44) which sequentially stores the parallel data subjected to thesecond decoding process and, thereafter, changes the order of the storeddata into the original order to read the data, and an information datareproduction unit (corresponding to a third multiplexing circuit 37 anda fourth multiplexing circuit 38) which multiplexes the read paralleldata to reproduce the original information data.

[0017] In the above-mentioned optical transmission system, combinations(corresponding to error correction sections 34 a, . . . , 34 b) eachconstituted by the first error correction unit, the third reading unit,the second error correction unit, and the fourth reading unit areconnected to each other in a plurality of stages.

[0018] The FEC multiplexing device according to another aspect of thepresent invention is provided on a transmission side of an opticaltransmission system. The FEC multiplexing device comprises a firstreading unit which sequentially stores parallel data generated bydemultiplexing information data and, thereafter, changes the order ofthe stored data on the basis of a predetermined standard to read thedata, a first encoding unit which performs first error correctionencoding to the read data to generate first error correction codes, asecond reading unit which sequentially stores the first error correctioncodes and, thereafter, changes the order of the stored data into theoriginal data to read the data, a second encoding unit which performssecond error correction encoding to the read data to generate seconderror correction codes, and a frame generation unit which multiplexesthe second error correction codes to generate an FEC frame.

[0019] The FEC demultiplexing device according to still another aspectof the present invention is provided on a reception side of atransmission system. The FEC demultiplexing device comprises a firsterror correction unit which performs error correction by a firstdecoding process to parallel data generated by demultiplexing an FECframe, a first reading unit which sequentially stores the parallel datasubjected to the first decoding process and, thereafter, changes theorder of the stored data on the basis of a predetermined standard toread the data, a second error correction unit which performs errorcorrection by a second decoding process to the read parallel data, asecond reading unit which sequentially stores the parallel datasubjected to the second decoding process and, thereafter, changes theorder of the stored data into the original order to read the data, andan information data reproduction unit which multiplexes the readparallel data to reproduce the original information data.

[0020] In the above-mentioned FEC demultiplexing device, combinationseach constituted by the first error correction unit, the first readingunit, the second error correction unit, and the second reading unit areconnected to each other in a plurality of stages.

[0021] The error correction method according to still another aspect ofthe present invention comprises the FEC generation step ofgenerating/outputting an FEC frame, and the error correction step ofperforming error correction by using the received FEC frame. The FECgeneration step includes the first parallel data generation step ofdemultiplexing information data, adding an OH (OverHead) data region andfirst and second redundant data regions to the demultiplexed informationdata, and inserting predetermined OH information into the OH data regionto generate first parallel data, the first reading step of sequentiallystoring the first parallel data and, thereafter, changes the order ofthe storage data on the basis of a predetermined standard to read thedata, the first encoding step of performing first error correctionencoding to the read data and storing the redundant information of thedata in the first redundant data region to generate to generate firsterror correction codes, the second reading step of sequentially storingthe first error correction codes and, thereafter, changes the order ofthe stored data into the original data to read the data, the secondencoding step of performing second error correction encoding to the readdata and storing the redundant information of the data in the secondredundant data region to generate second error correction codes, and theframe generation step of multiplexing the second error correction codesto generate an FEC frame. The error correction step includes the secondparallel data generation step of demultiplexing the FEC frame andestablishing frame synchronism after the demultiplexing to generatesecond parallel data, the first error correction step of performingerror correction by a first decoding process to the second paralleldata, the third reading step of sequentially storing the parallel datasubjected to the error correction and, thereafter, changes the order ofthe stored data on the basis of a predetermined standard to read thedata, the second error correction step of performing error correction bya second decoding process to the read parallel data, the fourth readingstep of sequentially storing the parallel data subjected to the errorcorrection and, thereafter, changes the order of the stored data intothe original order to read the data, and the information datareproduction step of separating the overhead information from the readparallel data, deleting the OH data regions and the redundant dataregions, and multiplexing the parallel data to reproduce the originalinformation data.

[0022] In the above-mentioned error correction method, in the errorcorrection step, a combination of processes performed by the first errorcorrection step, the third reading step, the second error correctionstep, and the fourth reading step is performed plural times.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023]FIG. 1 is a diagram showing the configuration of an opticaltransmission system according to one embodiment of the presentinvention,

[0024]FIG. 2 includes diagrams showing the configurations of an FECmultiplexing device and an FEC demultiplexing device in the opticaltransmission system,

[0025]FIG. 3 is a diagram showing the concept of an FEC frametransmitted between the FEC multiplexing circuit and the FECdemultiplexing circuit,

[0026]FIG. 4 is a diagram showing processing directions of a first errorcorrection code and a second error correction code,

[0027]FIG. 5 includes diagrams showing configurations of FEC frames,

[0028]FIG. 6 includes diagrams showing the configurations of an FECmultiplexing circuit and an FEC demultiplexing circuit in an opticaltransmission system,

[0029]FIG. 7 includes diagrams showing the configuration of aconventional FEC multiplexing device and a conventional FECdemultiplexing device, and

[0030]FIG. 8 includes diagrams showing the configuration of FEC framesgenerated by the conventional FEC multiplexing device.

BEST MODE FOR CARRYING OUT THE INVENTION

[0031] Embodiments of the optical transmission system according to thepresent invention will be described below with reference to theaccompanying drawings. This invention is not limited only to theembodiments described below.

[0032] First Embodiment:

[0033]FIG. 1 is a diagram showing the configuration of an opticaltransmission system according to the present invention. In FIG. 1,reference numeral 1 denotes a first light-receiving section, referencenumeral 2 denotes an FEC multiplexing circuit, reference numeral 3denotes a first light-transmitting section, reference numeral 4 denotesa optical transmission path, reference numeral 5 denotes a secondlight-receiving section, reference numeral 6 denotes an FECdemultiplexing circuit, and reference numeral 7 denotes a secondlight-transmitting section.

[0034] In this optical transmission system, the first light-receivingsection 1 receives an STM-16 optical signal, converts the optical signalinto an electric signal, and outputs the electric signal to the FECmultiplexing circuit 2. The FEC multiplexing circuit 2 demodulates thereceived electric signal from the first light-receiving section 1,performs processes such as insertion of OH information and FEC encoding,and performs multiplexing again to generate an FEC frame. The FECmultiplexing circuit 2 outputs the FEC frame to the firstlight-transmitting section 3. The first light-transmitting section 3converts the received FEC frame into an optical signal and transmits theoptical signal to the optical transmission path 4 constituted by anoptical fiber.

[0035] The second light-receiving section 5 which receives the opticalsignal from the optical transmission path 4 converts the optical signalinto an FEC frame of an electric signal, and outputs the converted FECframe to the FEC demultiplexing circuit 6. The FEC demultiplexingcircuit 6 demultiplexes the received FEC frame, performs processes suchas frame synchronism of the FEC frame, FEC decoding, and separation ofan OH, performs multiplexing, and generates (demodulates) the originalSTM-16 electric signal. The STM-16 electric signal is output to thesecond light-transmitting section 7. The second light-transmittingsection 7 converts the received electric signal into an optical signal,and outputs the STM-16 optical signal.

[0036] In the optical transmission path 4, since an optical SNR isdeteriorated due to long-distance and large-capacity transmission of anoptical signal, a large number of bit errors are generated in the FECframe converted into the electric signal by the second light-receivingsection 5, and the bit errors are corrected by the FEC demultiplexingcircuit 6. In this manner, a bit error rate of the STM-16 optical signalconverted into the optical signal by the second light-transmittingsection 7 can be improved, and communication service havingpredetermined quality can be provided.

[0037]FIG. 2 includes diagrams showing the configurations of the FECmultiplexing circuit 2 (see FIG. 2(a)) and the FEC demultiplexingcircuit 6 (see FIG. 2(b)) in the optical transmission system. In FIG.2(a), reference numeral 11 denotes a first demultiplexing circuit 11,reference numeral 12 denotes a second demultiplexing circuit, referencenumeral 13 denotes a first rate change circuit, reference numeral 14denotes a OH insertion circuit, reference numeral 15 denotes a firstmemory circuit, reference numeral 16 denotes a first RS encodingcircuit, reference numeral 17 denotes a second memory circuit, referencenumeral 18 denotes a second RS encoding circuit, reference numeral 19denotes a first multiplexing circuit, and reference numeral 20 denotes asecond multiplexing circuit. In FIG. 2(b), reference numeral 31 denotesa demultiplexing circuit, reference numeral 32 denotes a fourthdemultiplexing circuit, reference numeral 33 denotes a framesynchronizing circuit, reference numeral 34 denotes an error correctionsection, reference numeral 35 denotes an OH separation circuit,reference numeral 36 denotes a second rate change circuit, referencenumeral 37 denotes a third multiplexing circuit, reference numeral 38denotes a fourth multiplexing circuit, reference numeral 41 denotes afirst RS (240, 224) decoding circuit, reference numeral 42 denotes athird memory circuit, reference numeral 43 denotes a second RS (240,224) decoding circuit, reference numeral 44 denotes a fourth memorycircuit.

[0038] The operations of the FEC multiplexing circuit 2 and the FECdemultiplexing circuit 6 according to the present invention will bedescribed below with reference to the accompanying drawings. In the FECmultiplexing circuit 2 shown in FIG. 1, the first demultiplexing circuit11 demodulates STM-16 data (2.5 Gbit/s) received from the firstlight-receiving section 1 to generate 16 parallel data (156 Mbit/s), andoutputs the 16 generated parallel data to the second demultiplexingcircuit 12. The second demultiplexing circuit 12 demodulates the 16received parallel data (156 Mbit/s) into 128 parallel data (19 Mbit/s)and outputs the 128 parallel data to the first rate change circuit 13.

[0039] The first rate change circuit 13 adds OH data regions andredundant data regions to the 128 received parallel data (19 Mbit/s) togenerate 128 parallel data (22 Mbit/s), and output the 128 parallel datato the OH insertion circuit 14. The OH insertion circuit 14 insertsoverhead information (e.g., frame synchronous information or the like)required to maintain/operate the optical transmission system into the OHdata regions in the 128 received parallel data.

[0040] The first memory circuit 15 changes the order of the 128 paralleldata (22 Mbit/s) into which the pieces of overhead information areinserted to read the 128 parallel data, and outputs the 128 paralleldata the order of which is changed to the first RS (240, 224) encodingcircuit 16. The first RS (240, 224) encoding circuit 16 performs RS(240, 224) error correction encoding to the 128 received parallel datathe order of which is changed, stores the pieces of redundantinformation of the 128 parallel data in the redundant data regions, andoutputs the 128 encoded parallel data to the second memory circuit 17.

[0041] The second memory circuit 17 changes the order of the 128parallel data (22 Mbit/s) rearranged by the first memory circuit 15 intothe original order again to read the 128 parallel data, and outputs theparallel data to the second RS (240, 224) encoding circuit 18. Thesecond RS (240, 224) encoding circuit 18 performs RS (240, 224) errorcorrection encoding to the 128 parallel data the data of which ischanged into the original order, stores the redundant information of the128 parallel data in the redundant data regions, and outputs the 128encoded parallel data to the first multiplexing circuit 19.

[0042] The first multiplexing circuit 19 multiplexes the 128 receivedparallel data (22 Mbit/s) to generate 16 parallel data, and outputs the16 parallel data to the second multiplexing circuit 20. The secondmultiplexing circuit 20 further multiplexes the 16 received paralleldata to generate/output 2.86-Gbit/s FEC frame.

[0043] On the other hand, in the FEC demultiplexing circuit 6 shown inFIG. 1, the demultiplexing circuit 31 which receives the FEC framethrough the optical transmission path 4 demultiplexes the FEC frame togenerate 16 parallel data (179 Mbit/s), and outputs the 16 parallel datato the fourth demultiplexing circuit 32. The fourth demultiplexingcircuit 32 further demultiplexes the 16 received parallel data togenerate 128 parallel data (22 Mbit/s), and outputs the 128 paralleldata to the frame synchronizing circuit 33.

[0044] The frame synchronizing circuit 33 inspects frame synchronouspatterns stored in the OH data regions in the 128 received parallel datato detect the start position of the FEC frame, and establishesmulti-frame synchronism.

[0045] The first RS (240, 224) decoding circuit 41 performs a decodingprocess by RS (240, 224) codes to the 128 parallel data after the framesynchronism is established, corrects bit errors, and outputs the 128corrected parallel data to the third memory circuit 42. The third memorycircuit 42 changes the order of the 128 received parallel data (22Mbit/s) to read the 128 parallel data, and outputs the 128 parallel datathe order of which is changed to the second RS (240, 224) decodingcircuit 43.

[0046] The second RS (240, 224) decoding circuit 43 performs a decodingprocess by RS (240, 224) codes to the 128 parallel data the order ofwhich is changed, corrects bit errors, and outputs the 128 correctedparallel data to the fourth memory circuit 44. The fourth memory circuit44 changes the order of the 128 parallel data (22 Mbit/s) the order ofwhich is changed by the third memory circuit 42 to the original order toread the 128 parallel data. The 128 parallel data the order of which ischanged into the original order is output to the OH separation circuit35.

[0047] The OH separation circuit 35 separates OH from the 128 receivedparallel data, and outputs the 128 parallel data from which the OH areseparated to the second rate change circuit 36. The second rate changecircuit 36 deletes the OH data regions and the redundant data regionsfrom the 128 received parallel data (22 Mbit/s) to generate 128 paralleldata (19 Mbit/s), and outputs the 128 parallel data to the thirdmultiplexing circuit 37. The third multiplexing circuit 37 multiplexesthe 128 received parallel data (19 Mbit/s) to generate 16 parallel data(156 Mbit/s), and outputs the 16 parallel data to the fourthmultiplexing circuit 38. Finally, fourth multiplexing circuit 38 furthermultiplexes the 16 received parallel data to generate/output 2.5-Gbit/sSTM-16 data.

[0048]FIG. 3 is a diagram showing the concept of an FEC frametransmitted between the FEC multiplexing circuit 2 and the FECdemultiplexing circuit 6. The FEC frame employs the multi-frameconfiguration which is changed from a frame #1 to a frame #15. In thiscase, the first RS encoding circuit 16 and the second RS decodingcircuit 43 performs the processes of the frame #1 to the frame #15 bythe first error correction codes, and stores redundant data in theseprocesses in the frame #15. The second RS encoding circuit 18 and thefirst RS decoding circuit 41 perform processes in sections of frames bysecond error correction codes, and store the redundant data in theseprocesses in the ends of the frames.

[0049]FIG. 4 is a diagram showing processing directions of the firsterror correction code and the second error correction code. In the firstembodiment, as shown in FIG. 4, the processing directions of the firsterror correction code and the second error correction code are madedifferent from each other. For example, burst-like bit errors arediffused to improve error correction capability.

[0050] An error correction method using an FEC frame will be describedbelow. FIG. 5(a) is a diagram showing the configuration of the frames(#1 to #14) of the 128 parallel data (22 Mbit/s) output from the OHinsertion circuit 14. In this case, for example, OH data: OH 1 to 16 arestored in the OH data regions added by the first rate change circuit 13,and each of the sub-frames is constituted by one column of OH data, 223columns of STM-16 data, and 16 columns of second RS (240, 224) redundantdata regions. FIG. 5(b) is a diagram showing the configuration of theframe #15 of the 128 parallel data (22 Mbit/s) output from the OHinsertion circuit 14. This frame is constituted by the first and secondRS (240,224) redundant data regions. FIG. 5(c) is a diagram showing amethod of generating an FEC frame.

[0051] The first memory circuit 15 reads the 128 parallel data (22Mbit/s) which are sequentially stored in the memory and into which OHare inserted in the order named: the first column of the frame #1, thefirst column of the frame #2, . . . , the first column of the frame #15,the second column of the frame #1, the second column of the frame #2, .. . , the second column of the frame #15, . . . , the 224th column ofthe frame #1, the 224th column of the frame #2, . . . , the 224th columnof the frame #15. The first RS encoding circuit 16 performs RS encodingto the first column of the frame #1 the first column of the frame #2, .. . , the first frame of the frame #15, and stores the redundant data inthe first column of the frame #15. Subsequently, similarly, RS encodingis performed to the second column to the 224th column, and the redundantdata are stored in the corresponding columns of the frame #15. In thismanner, first RS (240, 224) codes 0 to 223 (128 parallel data outputfrom the first RS encoding circuit 16), and the first RS (240, 224)codes 0 to 223 are sequentially stored in the second memory circuit 17.

[0052] The second memory circuit 17 reads the frame #1 to the frame #14in the original order again, and outputs the read frames to the secondRS encoding circuit 18. The second RS encoding circuit 18 performs RSencoding to the read frames #1 to #14 every 8 sub-frames by using OHdata and STM-16 data as information data. The encoded redundant arestored in the second RS (240, 224) redundant regions, respectively, toconstitute second RS codes 0 to 15. Similarly, RS encoding is performedto the frame #15 every 8 sub-frames by using the first RS (240, 224)redundant data as information data. The encoded redundant data arestored in the second RS (240, 224) redundant data regions, respectively.In this manner, second RS codes 0 to 15 (128 parallel data output fromthe second RS encoding circuit 18) are generated and sequentiallyoutput.

[0053] Finally, the 128 parallel data (22 Mbit/s) output from the secondRS encoding circuit 18 are multiplexed by the first multiplexing circuit19 and the second multiplexing circuit 20. The second multiplexingcircuit 20 generates/outputs 2.86-Gbit/s FEC frame as the multiplexingresult. Reference symbol f (natural number) in FIG. 5(c) denotes thenumber of times of multiplexing of the RS (240, 224) codes 0 to 15. Thefirst embodiment shows a case in which f=16 is established. In the FECframe in the first embodiment, a transmission rate increases to 2.86Gbit/s which is (240, 224)×(15/14) times the transmission rate of theoriginal STM-16 data (corresponding to the OH data region and theredundant data region).

[0054] On the other hand, the first RS (240, 224) decoding circuit 41 ofthe FEC demultiplexing circuit 6 which receives the FEC frame performsRS (240, 224) decoding calculation to the 128 parallel data (22 Mbit/s)every 8 sub-frames to correct bit errors in the respective codes.However, when a large number of bit errors which are too many to becorrected are generated, bit errors are left in data output from thefirst RS decoding circuit 41 after only the decoding calculation isperformed.

[0055] Therefore, in the first embodiment, the second RS decodingcircuit 43 performs RS decoding calculation to the 128 parallel data (22Mbit/s) serving as the decoding result of the first RS decoding circuit41 in sections of columns of the frames #1 to #15 to also correct thebit errors left in the codes. In the first RS codes 0 to 223 and thesecond RS codes 0 to 15 in the first embodiment, as described above, theinformation data between the codes are rearranged and read. For thisreason, bit errors are diffused between the codes, and error correctioncapability can be considerably improved.

[0056] As described above, in the first embodiment, the FEC frameemploys a multi-frame configuration, and error correction encoding isperformed by a combination of different data having two directions. Forthis reason, burst bit errors can be diffused in comparison with theprior art in which error correction encoding is performed to data havingone direction. Therefore, error correction capability can beconsiderably improved. Since the improvement in error correctioncapability can be realized as described above, when the transmissionrate increases from 2.5 Gbit/s to 2.86 Gbit/s, an amount ofdeterioration of optical transmission characteristics can be madesmaller than that of the prior art. Therefore, a long-distance andlarge-capacity optical transmission system can be structured.

[0057] In the first embodiment, the first memory circuit 15 is arrangedon the input stage of the first RS (240, 224) encoding circuit 16, andthe second memory circuit 17 is arranged on the input stage of thesecond RS (240, 224) encoding circuit 18, so that the FEC frame can betransmitted without changing the order of the STM-16 data.

[0058] The first embodiment describes that RS (240,224) codes are usedas the first error correction codes, and the RS (240, 224) codes areused as the second error correction codes. However, the configuration isnot limited to the first embodiment. For example, the code length of theformer RS code may be represented by p1, an information data length maybe represented by q1, the code length of the later RS code may berepresented by p2, and an information data length may be represented byq2. In addition, the number of times of multiplexing may be representedby f, the number of multi-frames is represented by mf, the first errorcode and the second error code may be expressed by RS (p1, q1) codes andRS (p2, q2) code (p2=k1 (integer)×mf, q2=k2 (integer)×f, k1).

[0059] The first embodiment describes that OH of 1 bit is set for eachsub-frame. However, for example, OH of 2 or more bits may be set foreach sub-frame.

[0060] Second Embodiment:

[0061]FIG. 6 includes diagrams showing the configurations of an FECmultiplexing circuit 2 (see FIG. 6(a)) and an FEC demultiplexing circuit(see FIG. 6(b)) in the optical transmission system (see FIG. 1)described above as a second embodiment. In FIG. 6, each referencenumeral 34 a, 34 b denotes an error correction section. In the secondembodiment, a plurality of error correction sections 34 each arranged inthe FEC demultiplexing circuit 6 are arranged one after the other. Thesame reference numerals as in the first embodiment described abovedenote the same parts in second embodiment, and a description thereofwill be omitted.

[0062] In the second embodiment, the process performed by the errorcorrection section is repeated plural times. As a result, errorcorrection capability can be considerably improved in comparison withthe first embodiment. In the second embodiment, along-distance/large-capacity optical transmission system can be easilystructured without changing the configuration of the FEC frame andwithout changing the hardware configuration except that a plurality ofthe error correction sections are connected to each other one after theother.

[0063] Even in the second embodiment, in the same manner as in firstembodiment, the first error correction code and the second errorcorrection code can be expressed as an RS (p1, q1) code and an RS (p2,q2) code (p2=k1 (integer)×mf, q2=k2 (integer)×f, k1) . As in firstembodiment, OH having 2 or more bits may be set for each sub-frame.

[0064] As described above, according to the present invention, an FECframe employs a multi-frame configuration, and error correction encodingis performed by a combination of different data having two directions.For this reason, burst bit errors can be diffused in comparison with theprior art in which error correction encoding is performed to data havingone direction, and an optical transmission system which can considerablyimprove error correction capability can be advantageously obtained. Inaddition, since the improvement in error correction capability can berealized, even though the transmission rate increases, an amount ofdeterioration of optical transmission characteristics can be madesmaller than that of the prior art, and an optical transmission systemwhich can realize long-distance transmission and large-capacitytransmission can be advantageously obtained. The first reading unit isarranged on the input stage of the first encoding unit, and the secondreading unit is arranged on the input stage of the second encoding unit,so that an optical transmission system which can transmit an FEC framewithout changing the order of information data can be advantageouslyobtained.

[0065] According to the next invention, since the processes performed bythe first error correction unit, the third reading unit, the seconderror correction unit, and the fourth reading unit are repeated pluraltimes, an optical transmission system which can further considerablyimprove error correction capability can be advantageously obtained. Inaddition, a long-distance/large-capacity optical transmission system,which can be easily structured without changing the configuration of theFEC frame and without changing the hardware configuration except that aplurality of the error correction sections are connected to each otherone after the other, can be advantageously obtained.

[0066] According to the next invention, the FEC frame employs amulti-frame configuration, and error correction encoding is performed bya combination of different data having two directions. For this reason,burst bit errors can be diffused in comparison with the prior art inwhich error correction encoding is performed to data having onedirection, and an FEC multiplexing device which can considerably improveerror correction capability can be advantageously obtained. In addition,the first reading unit is arranged on the input stage of the firstencoding unit, and the second reading unit is arranged on the inputstage of the second encoding unit, so that an FEC multiplexing devicewhich can transmit an FEC frame without changing the order ofinformation data can be advantageously obtained.

[0067] According to the next invention, the FEC frame employs amulti-frame configuration, and error correction is performed by acombination of different data having two directions. For this reason, anFEC demultiplexing device which can considerably improve errorcorrection capability in comparison with the prior art in which errorcorrection is performed to data having one direction can beadvantageously obtained. In addition, since the improvement in errorcorrection capability can be realized, even though the transmission rateincreases, an amount of deterioration of optical transmissioncharacteristics can be made smaller than that of the prior art, and anFEC demultiplexing device which can structure a long-distance andlarge-capacity optical transmission system can be advantageouslyobtained.

[0068] According to the next invention, since the processes performed bythe first error correction unit, the first reading unit, the seconderror correction unit, and the second reading unit are repeated pluraltimes, an FEC demultiplexing device which can further considerablyimprove error correction capability can be advantageously obtained. Inaddition, an FEC demultiplexing device, which can easily structure along-distance/large-capacity optical transmission system withoutchanging the configuration of the FEC frame and without changing thehardware configuration except that the respective units are connected toeach other one after the other, can be advantageously obtained.

[0069] According to the next invention, the FEC frame employs amulti-frame configuration, and error correction encoding is performed bya combination of different data having two directions. For this reason,burst bit errors can be diffused in comparison with the prior art inwhich error correction encoding is performed to data having onedirection, and an error correction method which can considerably improveerror correction capability can be advantageously obtained.

[0070] According to the next invention, since the processes performed bythe first error correction step, the third reading step, the seconderror correction step, and the fourth reading step are repeated pluraltimes, an error correction method which can further considerably improveerror correction capability can be advantageously obtained.

INDUSTRIAL APPLICABILITY

[0071] As described above, the optical transmission system, the FECmultiplexing device, the FEC demultiplexing device, and the errorcorrection method according to the present invention are useful for anoptical transmission system which corrects bit errors by FEC (ForwardError Correction), and are suitable to improve error correctioncapability even if an amount of deterioration of optical transmissioncharacteristics increases by an increase in rate.

1. An optical transmission system comprising: an FEC generation sectionwhich generates and outputs an FEC frame; and an error correctionsection which performs error correction based on the FEC frame, whereinthe FEC generation section includes, a first reading unit whichsequentially stores first parallel data generated by demultiplexinginformation data and, thereafter, changes the order of the storage dataon the basis of a predetermined standard to read the data; a firstencoding unit which performs first error correction encoding to the readdata to generate first error correction codes; a second reading unitwhich sequentially stores the first error correction codes and,thereafter, changes the order of the stored data into the original datato read the data; a second encoding unit which performs second errorcorrection encoding to the read data to generate second error correctioncodes; and a frame generation unit which multiplexes the second errorcorrection codes to generate the FEC frame, and wherein the errorcorrection section includes, a first error correction unit whichperforms error correction by a first decoding process to second paralleldata generated by demultiplexing the FEC frame; a third reading unitwhich sequentially stores the parallel data subjected to the firstdecoding process and, thereafter, changes the order of the stored dataon the basis of a predetermined standard to read the data; a seconderror correction unit which performs error correction by a seconddecoding process to the read parallel data; a fourth reading unit whichsequentially stores the parallel data subjected to the second decodingprocess and, thereafter, changes the order of the stored data into theoriginal order to read the data; and an information data reproductionunit which multiplexes the read parallel data to reproduce the originalinformation data.
 2. The optical transmission system according to claim1, wherein combinations each constituted by the first error correctionunit, the third reading unit, the second error correction unit, and thefourth reading unit are connected to each other in a plurality ofstages.
 3. An FEC multiplexing device provided on a transmission side ofan optical transmission system, the FEC multiplexing device comprising:a first reading unit which sequentially stores parallel data generatedby demultiplexing information data and, thereafter, changes the order ofthe stored data on the basis of a predetermined standard to read thedata; a first encoding unit which performs first error correctionencoding to the read data to generate first error correction codes; asecond reading unit which sequentially stores the first error correctioncodes and, thereafter, changes the order of the stored data into theoriginal data to read the data; a second encoding unit which performssecond error correction encoding to the read data to generate seconderror correction codes; and a frame generation unit which multiplexesthe second error correction codes to generate an FEC frame.
 4. An FECdemultiplexing device provided on a reception side of a transmissionsystem, the FEC demultiplexing device comprising: a first errorcorrection unit which performs error correction by a first decodingprocess to parallel data generated by demultiplexing an FEC frame; afirst reading unit which sequentially stores the parallel data subjectedto the first decoding process and, thereafter, changes the order of thestored data on the basis of a predetermined standard to read the data; asecond error correction unit which performs error correction by a seconddecoding process to the read parallel data; a second reading unit whichsequentially stores the parallel data subjected to the second decodingprocess and, thereafter, changes the order of the stored data into theoriginal order to read the data; and an information data reproductionunit which multiplexes the read parallel data to reproduce the originalinformation data.
 5. The FEC demultiplexing device according to claim 4,wherein combinations each constituted by the first error correctionunit, the first reading unit, the second error correction unit, and thesecond reading unit are connected to each other in a plurality ofstages.
 6. An error correction method comprising: the FEC generationstep of generating and outputting an FEC frame; and the error correctionstep of performing error correction based on the FEC frame, wherein theFEC generation step includes, the first parallel data generation step ofdemultiplexing information data, adding an OH (OverHead) data region andfirst and second redundant data regions to the demultiplexed informationdata, and inserting predetermined OH information into the OH data regionto generate first parallel data; the first reading step of sequentiallystoring the first parallel data and, thereafter, changes the order ofthe storage data on the basis of a predetermined standard to read thedata; the first encoding step of performing first error correctionencoding to the read data and storing the redundant information of thedata in the first redundant data region to generate to generate firsterror correction codes; the second reading step of sequentially storingthe first error correction codes and, thereafter, changes the order ofthe stored data into the original data to read the data; the secondencoding step of performing second error correction encoding to the readdata and storing the redundant information of the data in the secondredundant data region to generate second error correction codes; and theframe generation step of multiplexing the second error correction codesto generate an FEC frame, and wherein the error correction stepincludes, the second parallel data generation step of demultiplexing theFEC frame and establishing frame synchronism after the demultiplexing togenerate second parallel data; the first error correction step ofperforming error correction by a first decoding process to the secondparallel data; the third reading step of sequentially storing theparallel data subjected to the error correction and, thereafter, changesthe order of the stored data on the basis of a predetermined standard toread the data; the second error correction step of performing errorcorrection by a second decoding process to the read parallel data; andthe fourth reading step of sequentially storing the parallel datasubjected to the error correction and, thereafter, changes the order ofthe stored data into the original order to read the data; and theinformation data reproduction step of separating the overheadinformation from the read parallel data, deleting the OH data regionsand the redundant data regions, and multiplexing the parallel data toreproduce the original information data.
 7. The error correction methodaccording to claim 6, wherein, in the error correction step, acombination of processes performed by the first error correction step,the third reading step, the second error correction step, and the fourthreading step is performed plural times.